The session with one servo. More...

#include <hitec_session.h>

Data Fields
hitec_image_t	image
hitec_plan_t	plan
uint8_t	diff [HITEC_SES_SET_BYTES]
	Bit a of byte a / 8, bit a % 8: address a differs after a write's read-back.
uint8_t	series
uint8_t	clock
uint8_t	in_mode
uint8_t	result
uint8_t	last_rx
uint8_t	fail_addr
uint8_t	tries
uint8_t	step_index
uint8_t	plan_result
uint16_t	done
uint16_t	total
uint16_t	off_ms
hitec_image_t	target
hitec_ses_step_t	step
uint8_t	todo [HITEC_SES_SET_BYTES]
uint32_t	t_mark
uint32_t	gap
uint8_t	op
uint8_t	phase
uint8_t	out
uint8_t	abort
uint8_t	gap_on
uint8_t	addr
uint8_t	power
uint8_t	compare
uint8_t	sent
uint8_t	unsure

Detailed Description

The session with one servo.

Field Documentation

◆ abort

uint8_t hitec_session_t::abort

1: abort when the result comes

◆ addr

uint8_t hitec_session_t::addr

the address of the step

◆ clock

uint8_t hitec_session_t::clock

hitec_ses_clock_t

◆ compare

uint8_t hitec_session_t::compare

1: the write compares with target

◆ done

uint16_t hitec_session_t::done

addresses read by the running read

◆ fail_addr

uint8_t hitec_session_t::fail_addr

the address of the read or write that failed

◆ gap

uint32_t hitec_session_t::gap

ticks from t_mark before the next step

◆ gap_on

uint8_t hitec_session_t::gap_on

1: gap counts

◆ image

hitec_image_t hitec_session_t::image

what the servo confirmed: entry, reads, read-back, classic writes answered + +; never a D series write alone. After a write that failed, what the servo may have changed is not known (hitec_session_write())

◆ in_mode

uint8_t hitec_session_t::in_mode

1: an entry succeeded; 0 from a leave

◆ last_rx

uint8_t hitec_session_t::last_rx

hitec_rx_t of the last decoded step

◆ off_ms

uint16_t hitec_session_t::off_ms

the supply off time of entry and leave

◆ op

uint8_t hitec_session_t::op

the operation that runs

◆ out

uint8_t hitec_session_t::out

1: step is handed out, no result yet

◆ phase

uint8_t hitec_session_t::phase

the step it is at

◆ plan

hitec_plan_t hitec_session_t::plan

the plan of the running or last write

◆ plan_result

uint8_t hitec_session_t::plan_result

hitec_plan_result_t of the last hitec_session_write()

◆ power

uint8_t hitec_session_t::power

D series entry: cycle the supply

◆ result

uint8_t hitec_session_t::result

hitec_ses_t of the last operation

◆ sent

uint8_t hitec_session_t::sent

1: a plan step was handed out and its result fed, whatever it was

◆ series

uint8_t hitec_session_t::series

hitec_family_t

◆ step

hitec_ses_step_t hitec_session_t::step

the step handed out

◆ step_index

uint8_t hitec_session_t::step_index

writes of the plan that took

◆ t_mark

uint32_t hitec_session_t::t_mark

clock at the last result

◆ target

hitec_image_t hitec_session_t::target

the image a write's read-back must hold

◆ todo

uint8_t hitec_session_t::todo[HITEC_SES_SET_BYTES]

addresses still to read

◆ total

uint16_t hitec_session_t::total

addresses it reads

◆ tries

uint8_t hitec_session_t::tries

tries of the running or last transaction

◆ unsure

uint8_t hitec_session_t::unsure

1: the plan step at step_index was fed a result and no + + confirmed it

The documentation for this struct was generated from the following file:

protocols/hitec/include/hitec_session.h

Data Fields